Slaved pcm clock circuit

ABSTRACT

In a frequency synchronized PCM transmission loop between a master switching exchange and slaved terminal equipment, a slaved PCM clock timing circuit is adjustable to alter the receive-totransmit time for the terminal equipment as a means of providing that the total loop transmission time delay is an integral multiple of the frame period. The transmit clock timing generator within the transmit section of the terminal equipment is eliminated and the slaved PCM clock circuit is provided with digit and channel blocking means for delaying the count of transmit digit and channel information until a predetermined relationship is attained between transmit digit and channel information and the received digit and channel information.

United States Patent [191 Pitroda et al.

[451 Apr. 30, 1974 SLAVED PCM CLOCK CIRCUIT Primary ExaminerRichardMurray [75] Inventors: Satyan G. Pitroda, Villa Park; Asslstqm JohnGodfrey Michael Kelly, Melrose Park; Attorney, Agent, or Firm-L. N.Arnold Bernard J. Rekiere, Addison, all of Ill. 57 ABSTRACT AssigneeiGTE A f Electric In a frequency synchronized PCM transmission loopLabomml'les Incorporated, between a master switching exchange and slavedter- Noflhlake, Ill. minal equipment, a slaved PCM clock timing circuitis [22] Filed: 23 1973 adjustable to alterthe receive-to-transmit timefor the terminal equipment as a means of providing that the PP NW ,283total loop transmission time delay is an integral multiple of the frameperiod. The transmit clock timing [52] us CL 178/695 R, 325/58, 179/15BS generator within the transmit section of the terminal 51 Int. Cl.H04] 7/00 equiPmem is eliminated and the slaved PCM 5 Field f S h 17 95R 53 95 DC; circuit iS provided With digit and channel blocking 179/15BS, 15 AL, 15 A0; 325/38 R, 53 means for delaying the count of transmitdigit and channel information until a predetermined relation- [56]References Cited ship is attained between transmit digit and channel in-UNITED STATES PATENTS formation and the received digit and channelinformat'o 3,057,962 10/1962 Mann et al l78/69.5 R l n 5 Claims, 2Drawing Figures SIGNAL Cl OUT I c24 37 CHANNEL x 6| IN PUT ea CHANNEL T43 COUNTER s j 46 BCFF BCF F RS I 35 V D K 44 X 53 SIGNAL I DIGIT T OUTcou NTER s E 1 BDFF CHANNEL Y D8 BDFF INPUT 9% RS HANNEL "Z- 5 IN PUTPCM IN DIGIT R CHANNEL R T|M|NG COUNTER COUNTER 4 EXIRACTORIATENTEDAPRZTO I914 $808,368

I 28K K PCM OUT @5 34? DIGIT T CHANNELT TIMING GENERATOR GENERATOR CLOCKTRANsMIT CLOCK RECEIVE I4 '1 22 PCM ELL REESICVKE DIGIT R 'CHANNEL RTIMING GENERATOR GENERATOR ExTRACTOR PCM TERMINAL EQUIPMENT (PRIOR ART)SIGNAL CI OUT P024 3? CHANNEL x INPUT 63 CHANNEL T COUNTER s 46 BCFFBCFF s I 35 V I DI A K 44 '1 SIGNAL I DIGIT T 1 OUT COUNTER I BDFFCHANNELY D8 BDFF/ INPUT CHANNELZ- 5 INPUT PCM IN C tg x OIGIT R CHANNELR TIMING COUNTER COUNTER l4 ExTRACTOR 1 SLAVED PCM CLOCK CIRCUITBACKGROUND This invention relates generally to master-slave timingsynchronization techniques in PCM communication net-works, and moreparticularly, relates to a slaved PCM clock circuit to be includedateach channel bank (terminal) equipment station.

A master PCM digital switching exchange may typically receive digitalinformation pulse trains originating from a plurality of remote locatedchannel bank equipment stations, respectively. The master switchingexchange must then assemble a composite digital pulse train from thereceived terminal pulse trains so that the composite pulse train can beswitched through the master switching exchange. It is popular to employa master-slave synchronization method of obtaining synchronous operationof the transmission and reception of digital pulse information over thetransmission loop between the master-switching exchange and a selectedterminal equipment station. Synchronous operation is provided througheliminating the independent deriva tion of clock timing signals in thetransmit section of the terminal equipment and instead, slaving thereference timing of the transmit section to the clock timing signals asgenerated in the master switching exchange and then reconstructed in thereceive section of the remote terminal equipment. These transmissionloops are said to be frequency synchronized when the frequencies of theclock oscillators of the remote terminal stations are slaved (derivedfrom) to the clock oscillator frequency within the master exchange.Moreover, as a particular type of frequency synchronization, when theoverall propagation or transmission time delay is equal to an integralmultiple of the frame period, the transmission loop is said to be framesynchronized. It is generally understood that frame synchronizedtransmission of data is required in order to minimize the informationstorage required by input data buffer equipment pro-. vided at themaster exchange.

The occurrence of time delays between the master and slaved stations isfundamental to transmission and is a function of well-known variablessuch as propagation distance, cable temperature, repeater jitter, etc.Further, there is a time delay inherent in the operation of the channelbank equipment itself which is also a part of the overall transmissionloop delay. Heretofore, input data buffer equipment has been provided inthe receive section of the master station for adjusting the overall loopdelay to equal an integral multiple of the frame period. It is theintent of the present invention to provide a means of adjusting thechannel bank time delay for establishing the overall loop delay to beequal to an integral multiple of the frame period.

Existing commercial channel bank equipment includes a receive sectionwherein the clock timing signals are extracted or derived from theincoming .PCM information received from the master exchange, and atransmit section which would ordinarily include a transmit clock timinggenerator for providing timing signals for inclusion with the outgoingPCM informa tion. In order to modify the existing commercial channelbanks to utilize master-slave synchronization techniques, the transmittiming signals could be slaved to the master clock timing signalsgenerated within the master exchange by an elaborate wiring arrangementwherein the transmit clock, digit transmit generator and channeltransmit generator are replaced. A lesser amount of wiring would berequired to so modify the terminal equipment through retaining the digittransmit and channel transmit generators and eliminating the transmitclock. However, the elimination of the transmit clock will result in apermanent timing offset between the digit and channel counts of thetransmit and receive sections since upon initial operation of thetransmission loop the random states of the counters within thesetransmit and receive sections will be preserved. Such an offset willadversely affect overall loop synchronization and can be eliminated byexternal reset means, if desired. However, it is proposed by the presentinvention to modify this offset within the terminal equipment byproviding a slaved PCM clock circuit therein which will adjust digit andchannel timing between the transmit and receive sections until apredetermined relationship between the digit and channel counters of thereceive and transmit sections is provided.

SUMMARY It is therefore among the objects of the present invention toprovide for master-slave timing synchronization between a master PCMswitching exchange and a remote terminal station; to provide forderiving the clock timing signals in the transmit section of theterminal equipment from the clock timing signals transmitted from themaster exchange and inputted to the receive section of the terminalequipment; to provide means for establishing a selected timing offset asrequired by the overall loop length whereby the advancement of thetransmit counters is blocked until the transmit digit and channelcounters are equal to the receive digit and channel counters; and toprovide for the slaving of terminal equipment with a minimum ofelectrical and mechanical alterations to existing terminal equipment.

A slaved PCM clock circuit comprises a receive clock timing extractorcircuit means for extracting master clock timing signals, both digit andchannel timing signals, from a pulse data train inputted to the terminalequipment. Receive and transmit digit counter means record reoccurringdigits and activate receive and transmit channel counter means after apredetermined number of digit timing signals are counted, respectively.First and second counter blocking means are associated with the transmitdigit and channel counter means, respectively, for preventing theadvancement of these counter means until predetermined counter stateshave been obtained by the sequentially advancing receive digit andchannel counter means.

THE DRAWING FIG. 1 is a functional representation of the clock transmitand clock receive sections of prior art PCM terminal equipment; and FIG.2 is partly a schematic and partly a functional representation of aslaved PCM clock circuit for use with such PCM terminal equipment inaccordance with the present invention.

DETAILED DESCRIPTION FIG. 1 shows the prior art manner of providingclock transmit and clock receive timing signals withinthe separatetransmit l0 and receive 12 sections of a PCM channel bank (terminal)equipment. Existing D1 and D2 channel bank equipment can utilize asynchronization technique wherein the clock receive timing signals arederived from an incoming PCM pulse data train 14 outputt'ed to theterminal equipment from a master PCM digital switching exchange (notshown). For this purpose, there is shown in FIG. 1 a receive clocktiming extractor circuit 21 which extracts timing information from theincoming PCM pulse train 14 and thereafter, the appropriate digit (bit)and channel clock timing signals are established by digit R and channelR generator circuits 23 and 25, respectively. In the transmit section ofthe terminal. equipment, the clock transmit timing signals areindependently generated through providing a transmit clock timingcircuit 27, a digit T generator 28 and a channel T generator 29, and theresulting clock pulses then inserted into an outgoing PCM pulse datatrain 34 provided to the master switching exchange.

In providing for a master-slave synchronization relationship between thetiming operation of the remote terminal equipment and the masterswitching exchange, a slaved PCM clock circuit 20 as shown in FIG. 2 isutilized. Essentially, the receive clock timing extractor circuit 21 isretained and the master clock timfrom further advancing. Now, when thedigit R counter 31 reaches count eight, the BDFF circuit 53 is reset andthe digit T counter is enabled to advance sequentially simultaneouslywith the digit R counter with each incoming clock pulse.

It can be seen that a similar operation can be employed to obtainalignment of channels for theclock receive 12 and clock transmitsections of the terminal equipment. The channel blocking circuit means43 is used to align the channel R and T counter circuits 33 and 37.Accordingly, a channel blocking flip-flop count, for example, channel Y,which resets the BCFF ing signals as derived from the PCM IN pulse train14 are utilized in both the transmit T and receive R sections of theterminal equipment. As the repeating clock pulses representing thedigit, channel and frame period format of the PCM pulse train 14 isreceived and extracted, digit R counter circuit 31 counts the number ofbit periods and when a preselected count such as 8 bits is reached, thecounter 31 inputs a channel R counter 33 for recording the occurrence ofa channel period.

Now also shown in FIG. 2 is a digit T counter circuit 35, a channel Tcounter circuit 37 and a pair of counter blocking circuit means 41 and43 associated therewith, respectively. In the operation of the slavedPCM clock circuit 20, a Z-input NAND logic gate 51 prevents theadvancement of the digit T counter 35 until such time as the gate 51 isactivated by the presence of a BDFF signal occurring simultaneously withthe occurrence of a digit timing signal (clock pulse)from the receiveextractor circuit 21. The BDFF signal is the reset RS output of a digitblocking flip-flop BDFF circuit 53. The BDFF circuit 53 is set S by thedual occurrence of in- I puts from the digit T counter 35 and apreselected channelcount shown as channel Z input for purposes ofillustration. The BDFF circuit 53 is reset by the dual occurrence ofinputs from the digit R counter 31 and the channel Z input. Thecombination of the logic gate 51, the set and reset logic gates and theBDFF circuit 53 compose a transmit digit counter blocking circuit meansfor preventing the regular advancement of the digit T counter 35 untilthe digit R counter has advanced to a predetermined digit count.

The digit counter blocking circuit means 41 is useful to align the digitR and T counter circuits 31 and 35 so that each reach count eight andgive an output at substantially the same time. Since the digit R and Tcounters 31 and 35 are more likely in a-random state of 1 to 8 at theoutset of any given reception and transmittal of PCM data, the use ofthe same clock pulse without adjustment would result in an offset in thecounters and a non-synchronous operation. if the blocking flip-flopcircuit 53 is set by the eighth count of the digit T counter 35, theBDFF output is absent, the logic gate 51 is disabled and the digit Tcounter 35 is prevented circuit 63. Thereafter, the channel R and Tcounter circuits 33 and 37 advance together with each 8 digit count.

In the event that the digit R and digit T counters 31 and havemisaligned counting states, the digit T counter 35 is disabled untildigit R counter 31 provides an output signal during the occurrence ofthe prese- V lected channel time Z. A 2-input logic gate 42 is thenenabled and the BDFF circuit 53 is reset. Then, the digit T counter 35is enabled to advance synchronously with the digit R counter 31. It isto be noted that when the counter 35 counts during channel time Z, a2-input logic gate 44 is enabled and would provide a signal to set theset-reset circuit 53 except that the logic gate 42 is also enabled atthis time. Hence, the set-reset circuit 53 is designed so as not torespond to change its state from the reset condition; If at any time thedigit R counter 3] fails to provide the eighth count during the channeltime Z, the BDFF circuit 53 is then set and the digit T counter 35 isprevented from advancing until digit R counter again provides the outputsignal during the channel time Z.

With respect to the operation of the channel blocking circuit means 43,when the channel R counter 33 counts channel Y the BCFF circuit 63 isreset and the channel T counter 37 is allowed to advance synchronouslywith the counter 33. The output signal of the channel T counter 37 isconveniently identified as a channel X signal, and so long as channel Xoccurs simultaneously with channel Y in a synchronous timing pattern,the BCFF circuit 63 will remain reset. If at any time the channel timesX and Y become misaligned with respect to time, the BCFF circuit 63 isset and the channel T counter 37 is prevented from advancing.

Further, it should be noted that by selecting different receive channelsto reset the BCFF circuit 63, any desired channel time delay period canbe introduced into the operation of the terminal equipment. Obviously,any desired digit time delay period can be realized by merely selectingdifferent receive digits to reset the BDFF circuit 53. As an example, ifa selected transmission loop required, in order to obtain an overallloop delay which was an integral multiple of frames, a loop delay of 20channels and four digit (bit) positions, the BCFF circuit 63 could beset by transmit channel one and reset by receive channel 21. The BDFFcircuit 53 could be set by transmit digit'l and reset by receive digit5.

The above described digit alignment procedure could well be repeatedcontinuously so as to set and reset the BDFF circuit 53 every receivechannel which is to be in alignment with the transmit channel. However,the framing digit appearing every twenty-fourth transmit channelcomprises a ninth digit which will offset digit matching until thereceive digit nine appears. To pre vent this misalignment, digitmatching is performed every frame during any known channel wherein thedigits are supposed to be aligned. Through the use of channel and digitoffset techniques herein described, a maximum transmission loop delay ofone frame period can be obtained from the remote terminal equipment.

In D2 type terminal equipment having on-hook, offhook signaling beingproduced every twelfth frame period and wherein the loop delay is anintegral multiple of either six or 12 frames, there may be required thatan offset be provided in the occurrence of the receive and transmitframe periods and a signaling frame be generated at the transmit sectionunder the control of the receive frame. In a manner similar to the digitand channel blocking circuit means, a blocking frame flipflop BFFFcircuit can be added to the circuit of FIG. 2.

The implementation of the applicants slaved PCM clock circuit requires aminimum of electrical and mechanical alterations and modifications toexisting terminal equipment. The invention thereof obviates bulky delayline arrangements and associated driving circuitry or large bufferstorage in the transmission loop. Instead, the invention provides anovel means of producing the required transmission loop delay by channeland digit offset between the receive and transmit sections of theterminal equipment. Further, the built-in loop delay is alterable withminimum wiring modifications.

What is claimed is:

l. A clock timing circuit for use with a frequency synchronizedtransmission PCM carrier loop extending between a slaved channel bankequipment station and a master PCM switching exchange station, saidclock circuit comprising: receive clock timing circuit means at saidchannel bank equipment station for extracting reoccurring first clocktiming signals from carried PCM pulse data received from said masterstation, receive digit and channel counter means and transmit digit andchannel counter means connected to said receive clock circuit means forsequentially counting said first clock timing signals, respectively,digit and channel counter blocking circuit means electrically interposedbetween said receive and said transmit digit and channel counter means,respectively, for blocking'the count advancement of said transmit digitand channel counter means until predetermined digit and channel countsare provided by said receive digit and channel counter means,respectively, whereby preselected timing offsets are provided betweensaid receive and said transmit digit and channel counter means,respectively.

2. A clock timing circuit as claimed in claim 1 wherein said digitcounter blocking circuit means is comprised of a set-reset logic circuitproviding a first output signal when said logic circuit is reset, firstgating means connected to enable said transmit digit counter means upondual signal reception of the first output signal from said logic circuitand one of said clock timing signals, and second gating means connectedto enable said logic circuit to reset upon the exclusive occurrence of afirst output signal from said receive digitcounter means during aselected channel time period and to set upon the exclusive occurrence ofa first output signal from said transmit digit counter means during saidselected channel time period. V

3. A clock timing circuit as claimed in claim 2 wherein said channelcounter blocking circuit means is comprised of another set-reset logiccircuit providing a first output signal when said other logic circuit isreset, third gating means connected to enable said transmit channelcounter means upon dual signal reception of the first output signal fromsaid other logic circuit and a first output signal from said transmitdigit counter means, and fourth gating means connected to enable saidother logic circuit to reset upon the exclusive occurrence of an outputsignal from said receive channel counter means and to set upon theexclusive occurrence of an output signal from said transmit channelcounter means.

4. A clock timing circuit as claimed in claim 3 wherein said first andthird gating means comprise 2- input NAND logic gates, respectively,said second gating means comprises a pair of Z-input NAND logic gates,one of which receives said first output signal from said receive digitcounter means and a predeter-. mined channel time signal and the otherof which receives the first output signal from said transmit digitcounter means and said predetermined channel time signal, and saidfourth gating. means includes a direct connection of said output signalfrom said receive channel counter means to the reset input of said otherlogic circuit and a 2-input NAND logic gatefor receiving said outputsignals from said receive and said transmit channel counter means.

5. A clock timing circuit for use with channel bank equipment incommunication with a PCM switching exchange by means of a PCM carriercommunication loop employing master-slave synchronization of transmitteddata, said clock circuit comprising: receive clock timing circuit meansfor receiving incoming PCM pulse data to said channel bank equipment andextracting therefrom reoccurring clock timing signals, rereceive digitand channel counter means and transmit digit and channel counter meansfor sequentially counting said clock timing signals, said transmitcounter means providing output digit and channel timing signals forinclusion in the transmitted data from said channel bank equipment, anddigit and channel counter blocking circuit means having gating meansthrough which said transmit digit and channel counter means receive saidreoccurring clock timing signals, respectively, andfurther having meansfor blocking said gating means from passing said reoccurring clocktiming signals to said transmit digit and channel counter means untilpredetermined digit and channel counts are provided by said receivedigit and channel counter means, respectively, whereby a variable timedelay is provided between the data receive time and the data transmittime of said channel bank equipment.

* It t

1. A clock timing circuit for use with a frequency synchronizedtransmission PCM carrier loop extending between a slaved channel bankequipment station and a master PCM switching exchange station, saidclock circuit comprising: receive clock timing circuit means at saidchannel bank equipment station for extracting reoccurring first clocktiming signals from carried PCM pulse data received from said masterstation, receive digit and channel counter means and transmit digit andchannel counter means connected to said receive clock circuit means forsequentially counting said first clock timing signals, respectively,digit and channel counter blocking circuit means electrically interposedbetween said receive and said transmit digit and channel counter means,respectively, for blocking the count advancement of said transmit digitand channel counter means until predetermined digit and channel countsare provided by said receive digit and channel counter means,respectively, whereby preselected timing offsets are provided betweensaid receive and said transmit digit and channel counter means,respectively.
 2. A clock timing circuit as claimed in claim 1 whereinsaid digit counter blocking circuit means is comprised of a set-resetlogic circuit providing a first output signal when said logic circuit isreset, first gating means connected to enable said transmit digitcounter means upon dual signal reception of the first output signal fromsaid logic circuit and one of said clock timing signals, and secondgating means connected to enable said logic circuit to reset upon theexclusive occurrence of a first output signal from said receive digitcounter means during a selected channel time period and to set upon theexclusive occurrence of a first output signal from said transmit digitcounter means during said selected channel time period.
 3. A clocktiming circuit as claimed in claim 2 wherein said channel counterblocking circuit means is comprised of another set-reset logic circuitproviding a first output signal when said other logic circuit is reset,third gating means connected to enable said transmit channel countermeans upon dual signal reception of the first output signal from saidother logic circuit and a first output signal from said transmit digitcounter means, and fourth gating means connected to enable said otherlogic circuit to reset upon the exclusive occurrence of an output signalfrom said receive channel counter means and to set upon the exclusiveoccurrence of an output signal from said transmit channel counter means.4. A clock timing circuit as claimed in claim 3 wherein said first andthird gating means comprise 2-input NAND logic gates, respectively, saidsecond gating means comprises a pair of 2-input NAND logic gates, one ofwhich receives said first output signal from said receive digit countermeans and a predetermined channel time signal and the other of whichreceives the first output signal from said transmit digit counter meansand said predetermined channel time signal, and said fourth gating meansincludes a direct connection of said output signal from said rEceivechannel counter means to the reset input of said other logic circuit anda 2-input NAND logic gate for receiving said output signals from saidreceive and said transmit channel counter means.
 5. A clock timingcircuit for use with channel bank equipment in communication with a PCMswitching exchange by means of a PCM carrier communication loopemploying master-slave synchronization of transmitted data, said clockcircuit comprising: receive clock timing circuit means for receivingincoming PCM pulse data to said channel bank equipment and extractingtherefrom reoccurring clock timing signals, rereceive digit and channelcounter means and transmit digit and channel counter means forsequentially counting said clock timing signals, said transmit countermeans providing output digit and channel timing signals for inclusion inthe transmitted data from said channel bank equipment, and digit andchannel counter blocking circuit means having gating means through whichsaid transmit digit and channel counter means receive said reoccurringclock timing signals, respectively, and further having means forblocking said gating means from passing said reoccurring clock timingsignals to said transmit digit and channel counter means untilpredetermined digit and channel counts are provided by said receivedigit and channel counter means, respectively, whereby a variable timedelay is provided between the data receive time and the data transmittime of said channel bank equipment.